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NAND flash reliability: Concerns associated with process geometry

Dennis Martin, president of Demartek, discusses NAND flash reliability concerns associated with process geometry in this Expert Response.

As NAND flash has scaled down from a process geometry of more than 50 nanometers to about 20nm, the endurance and

performance have gotten worse. So far, the manufacturers have been able to make up for it. How concerned should we be with NAND flash reliability as the process geometry sinks below 20nm?

As the process geometry goes below 20nm, things get more difficult to do because fewer electrons are available per floating gate transistor, resulting in decreased write throughput and endurance as the die sizes decrease.

However, manufacturers are finding new ways to decrease the die size while producing usable flash media by using 3D die stacking, increased ECC, advanced page mapping and other techniques. We’re getting close to some physical limits, but the engineers are still finding things that can be done.

This was first published in January 2012

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