NAND flash reliability: Concerns associated with process geometry

As NAND flash has scaled down from a process geometry of more than 50 nanometers to about 20nm, the endurance and performance have gotten worse. So far, the manufacturers have been able to make up for it. How concerned should we be with NAND flash reliability as the process geometry sinks below 20nm?

Requires Free Membership to View

As the process geometry goes below 20nm, things get more difficult to do because fewer electrons are available per floating gate transistor, resulting in decreased write throughput and endurance as the die sizes decrease.

However, manufacturers are finding new ways to decrease the die size while producing usable flash media by using 3D die stacking, increased ECC, advanced page mapping and other techniques. We’re getting close to some physical limits, but the engineers are still finding things that can be done.

This was first published in January 2012

There are Comments. Add yours.

TIP: Want to include a code block in your comment? Use <pre> or <code> tags around the desired text. Ex: <code>insert code</code>

REGISTER or login:

Forgot Password?
By submitting you agree to receive email from TechTarget and its partners. If you reside outside of the United States, you consent to having your personal data transferred to and processed in the United States. Privacy
Sort by: OldestNewest

Forgot Password?

No problem! Submit your e-mail address below. We'll send you an email containing your password.

Your password has been sent to: