Definition

NAND flash wear-out

This definition is part of our Essential Guide: Essential guide to the all-flash array market
Contributor(s): Carol Sliwa

NAND flash wear-out is the erosion of a NAND flash memory cell due to the repeated program/erase process necessary to write new data to a chip.

All of the bits in a NAND flash block must be erased before the data is written, or programmed. The program/erase process eventually breaks down the oxide layer within the floating-gate transistors of the NAND flash.

NAND flash uses a series of floating-gate transistors to store charge for an extended period of time. The oxide layer insulates the floating gate and traps the electrons, which control the switch-on voltage of the floating gate. The gradual deterioration of the oxide insulation can distort the manufacturer-set threshold value at which a zero or one is determined.

The NAND flash wear-out figures that the industry typically cites are 100,000 program/erase (P/E) cycles for single-level cell (SLC) flash, 30,000 P/E cycles for enterprise multilevel cell (eMLC) flash and 10,000 or fewer P/E cycles for multilevel cell (MLC) flash. Manufacturers have attempted to mitigate the wear-out factor through advancements in their product architectures, algorithms and controllers.

This was last updated in January 2012

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