Marvell's 88SS107 controller, the company's fifth iteration, will use a standard 6 Gbps SATA disk interface and features its branded low-density parity check decoding technology for detecting "crosstalk" errors. Marvell engineered the controller with 28-nanometer complementary metal-oxide semiconductor (CMOS) technology for more robust firmware.
"That allows us to put more circuitry into the chip and therefore enable more algorithms," Marvell CTO Zining Wu said.
TLC stores three bits of data per cell and is widely used in consumer drives that don't need high write cycles. Although less expensive than both single-level cell and multi-level cell flash (MLC), TLC is not used in enterprises due to its lower write endurance and signal interference caused by the three different voltage levels.
The more bits that are added per cell, the greater the chance that read/write disturbance will occur as adjacent cell voltages interfere with one another. TLC has a typical write endurance of 200 to 300 cycles per physical block of memory before its performance begins to degrade. MLC, which is the most popular form of flash memory in existing storage arrays, has a write endurance of about 3,000 cycles per physical memory block.
Marvell's advanced controller could lower total storage costs by enabling TLC to be integrated in place of MLC in SSDs, Wu said, although he declined to speculate how soon drive manufacturers will do so.
Arun Taneja, president of The Taneja Group, said Marvell's new controller should accelerate TLC flash in enterprise storage.
"Triple cell is going to start getting used in arrays for less-than-mission-critical applications, but even that is phenomenal news compared to where the industry was just two years ago, when there were no error-correcting algorithms to distinguish between one voltage level and another," Taneja said.
"To me, it's definitely big news because all cold storage is based on SATA spinning drives. And what's the biggest issue in very large archives? The costs of power, cooling and space," which would be reduced with increased use of TLC, Taneja said.
Marvell said its controller will be compatible with leading NAND manufacturers and is being sampled by SSD makers this summer.