Mangstor unveils MX6000 flash device with MRAM for persistent storage

Mangstor MX6000 will integrate Spin Torque MRAM (ST-RAM) on PCIe cards to enable in-storage processing instead of DRAM for persistent memory storage.

Mangstor Inc. has previewed its first product -- the MX6000 series of solid-state block storage devices -- using magneto-resistive random access memory from Everspin Technologies to perform secure data writes to NAND flash and move flash processing off of servers.

Mangstor will buy EMD3D064M Spin Torque 64 MB technology (ST-MRAM) from Everspin and integrate the persistent memory chips in the MX6000 line, scheduled for general availability in January 2015.

The two companies began collaborating in 2012, and the partnership will bring ST-MRAM into high-performance storage systems. Everspin has been shipping its first-generation MRAM to original equipment makers (OEMs) since 2009 for integration in storage controllers and arrays, with partners including Dell Inc. and Avago Technologies' LSI Corp.

Dynamic random access memory (DRAM) also is configurable as persistent memory, but it requires resistors and additional logic circuitry to furnish continuous power to volatile write buffers when a system is powered down. The extra componentry is a limiting factor of DRAM for persistent storage, sparking renewed interest in MRAM. Unlike flash, MRAM is not subject to wear factors that degrade performance.

We're not (pushing) dollars per gigabit. We're going for performance.
Trevor SmithCEO, Mangstor

Launching a flagship product based on MRAM signals an aggressive push into the market by Mangstor and broadens Everspin's footprint, said James Bagley, a senior analyst at Storage Strategies Now.

"It puts a stake in the ground that MRAM is something you could reliably use for persistent memory, other than DRAM with a battery or capacitor," Bagley said.

Mangstor NVMe drives are PCIe 3.0 compatible

The Mangstor NVMe drives are compatible with the PCI Express (PCIe) 3.0 protocol and use controllers by Altera Corp. Everspin said certification testing with modified Altera controllers is under way.

Mangstor uses 19-nanometer MLC NAND flash as main memory and integrates a small amount of MRAM as a circular write buffer to rapidly acknowledge writes and eliminate the need for super capacitors. 

The ST-MRAM-enabled MX6000 will be available in half-height and standard form factors. The half-height card includes 3 TB of raw storage, with usable capacity ranging from 1.5 TB to 2 TB. The full-height card provides up to 4 TB of raw storage and 2.7 TB of usable capacity. A third card is under development and expected to top out at 5.4 TB of raw storage.

Mangstor rates the MX6000 for up to one million random read IOPS and 600,000 random write IOPS, with 4 Gbps bandwidth for workloads that require high-performance storage. OEMs and resellers are sampling the device. Early use cases include accelerating database applications and virtual desktop infrastructure.

The device architecture includes a programmable 100-core processor and software intelligence to optimize flash channels and issue error correction. Two-thirds (67) of the processor cores are dedicated to controlling commands in the flash for garbage collection, wear leveling and logical-to-physical flash translation. The remaining cores handle in-storage processing, such as native key value lookups to accelerate memory cache or database searches.

"Ours is an enterprise-level drive. We're not [pushing] dollars per gigabit. We're going for performance," Mangstor CEO Trevor Smith said.

SanDisk Corp.'s Fusion-io, is the leading PCIe vendor. Fusion-cards use the server processors to manage flash translation and process transactions, requiring custom driver software. The MX6000 cards include "in-box" software drivers that run on the server and send NVMe commands across the PCIe bus. Processors execute the commands and use flash controls to decide when data gets written from write buffers to flash.

"Our differentiator is in moving the processing power closer to the data. Because we've moved the processing off the server, we don't use any host resources. What we've done is move that functionality closer to the processor, located next to the flash across the PCI Express bus," Smith said.

Spin Torque technology maximizes MRAM

Everspin's proprietary 64 MB Spin Torque technology refers to its method for gating the electrical current on each bit. The chips are stacked in a vertical plane to increase cell density and take advantage of MRAM as a persistent source of memory. ST-MRAM is designed to protect data in flight by writing data to write buffers, then securing it and signaling the host processor when the buffer is ready to receive new data. The data gets written later from write buffers directly to flash memory.

Everspin launched ST-MRAM as its next-gen MRAM in 2013 and started sampling to vendors in 2012.

"Even though we knew it was going to take us a little time to get to production level, our strategy was to feed the market early to help get the ecosystem in place. We wanted people to start playing with MRAM and see how it affects performance," Everspin CEO Phil LoPresti said.

The 64 MB version of ST-MRAM is an entry-level product geared for buffering, caching hard drives or adding solid-state drives. Everspin's product roadmap envisions 256 MB ST-MRAM being available in 2016, with a 1 GB option slated to hit the market by 2017.

For the 64 MB, Everspin buys partially processed complementary metal-oxide semiconductor (CMOS) wafers and then completes back-end magnetics integration at Everspin's production line in Chandler, Arizona. 

For the larger-capacity products,  LoPresti said Everspin is “very close” to finalizing an agreement with a 300-millimeter fab partner that would perform back-end processing on its CMOS production line.

Mangstor has not disclosed pricing for the MX6000 and said it is working on lining up OEMs as distribution channel partners.

Next Steps

New memory technologies emerge as successors to NAND flash

Spin transfer torque memory properties, benefits

Dig deeper on Server-based SSD implementations

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